Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE

ISBN-13: 9789048176533 / Angielski / Miękka / 2010 / 516 str.

Rudy Lauwereins;Jan Madsen

Opis

The Design Automation and Test in Europe, DATE, is Europe s leading international electronic systems design conference for electronic design, automation and test, from system level hardware and software implementation right down to integrated circuit design. It combines the conference with Europe s leading international ex- bition for electronic design, automation and test. To celebrate the tenth anniversary of DATE, we have compiled this book with the aim to highlight some of the most influential technical contributions from ten years of DATE. Selecting 30 papers, only 3 papers from each year, is a challenging endeavor. Although the impact of papers from the first years of DATE can be det- mined through various citation indexes, the impact from the later years still have to be seen. Together with all 10 Program Chairs, we have made a selection of the most influential papers covering the very broad range of topics which is characteristic for DATE."

Spis treści

Introduction; Rudy Lauwereins, Jan Madsen Section 1: System Level Design Introduction: System Level Design: Past, Present and Future; Daniel D. Gajski Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems; P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, and P. Pop, DATE1998 EXPRESSION: A language for architecture exploration through compiler/simulator retargetability; A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, A. Nicolau, DATE1999 RTOS Modeling For System Level Design; A. Gerstlauer, H. Yu, D.D. Gajski, DATE2003 Context-aware performance analysis for efficient embedded system design; M. Jersak, R. Henia, R. Ernst, DATE2004 On Lock-Free Synchronization for Dynamic Embedded Real-Time Software; H. Cho, .B Ravindran, E.D. Jensen, DATE2006 What If You Could Design Tomorrow’s System Today? N. Wingen, DATE2007 Section 2: Networks on Chip Introduction: Networks on Chip; Giovanni De Micheli A generic architecture for on-chip packet- switched interconnections; P. Guerrier, A. Greiner, DATE2000 Trade Offs In The Design Of A Router With Both Guaranteed And Best-Effort Services For Networks On Chip; E. Rijpkema, K.G.W. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander, DATE2003 Exploiting The Routing Flexibility For Energy-Performance Aware Mapping Of Regular Noc Architectures; J. Hu, R. Marculescu, DATE2003 xpipesCompiler: A tool for instantiating application specific Networks on Chip; A. Jalabert, S. Murali, L. Benini, G. De Micheli,DATE2004 Network traffic generator model for fast network-on-chip simulation; S. Mahadevan, F. Angiolini, M. Storoaard, R.G. Olsen, J. Sparsoe, J. Madsen, DATE2005 Section 3: Modeling, Simulation and Run-Time Management Introduction: Modeling, Simulation and Run-Time Management; Enrico Macii Dynamic power management for non-stationary service requests; E.Y. Chung, L. Benini, A. Bogiolo, G. De Micheli, DATE1999 Quantitative comparison of power management algorithms; Y. Lu, E. Chung, T. Simunic, L. Benini, G. De Micheli, DATE2000 Energy efficiency of the IEEE 802.15. 4 standard in dense wireless microsensor networks: modeling and improvement perspectives; B. Bougard, F. Catthoor, D.C. Daly, A. Chandrakasan, W. Dehaene, DATE2005 Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application; A. Singhee, R.A. Rutenbar, DATE2007 Compositional Specification of Behavioral Semantics; K. Chen, J. Sztipanovits and S. Neem, DATE2007 Section 4: Design technology for advanced digital systems in CMOS and beyond Introduction: Design technology for advanced digital systems in CMOS and beyond; Hugo De Man Address Bus Encoding Techniques for System-Level Power Optimization; L. Benini, G. De Micheli, E. Maccii, D. Sciuto, and C. Silvano, DATE1998 MOCSYN: Multiobjective core-based single-chip system synthesis; R.P. Dick, N.K. Jha, DATE1999 Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor; G. Quan and X. Hu, DATE2002 Synthesis

O autorze

Dr. Rudy Lauwereins is the General Chair for DATE 2007, Dr. Jan Madsen is the Technical Chair.

Blurb

The Design, Automation and Test in Europe (DATE) conference celebrated in 2007 its tenth anniversary. As a tribute to the chip and system-level design and design technology community, this book presents a compilation of the three most influential papers of each year. This provides an excellent historical overview of the evolution of a domain that contributed substantially to the growth and competitiveness of the circuit electronics and systems industry.

The papers were grouped in six sections:

• System Level Design;
• Networks on Chip;
• Modeling, Simulation and Run-Time Management;
• Digital Systems in CMOS and Beyond;
• Physical Design and Validation; and
• Test and Verification.

The winners of the prestigious EDAA Lifetime Achievement Award as well as other recognized experts in their field wrote an introduction to each section, summarizing the history in their domain and indicating how the selected DATE papers contributed to it.