DESIGN OF DIGIT-SERIAL FIR FILTER ALGORITHAMS, ARCHITECTURE & CAD TOOL

ISBN-13: 9786204202983 / Angielski / Miękka / 100 str.

K. Shashidhar

Opis

The multiplication of filter coefficients with the input data is generally implemented under a shift adds architecture, where each constant multiplication is realized using addition/subtraction and shift operations in an operation taking advantage in bit-parallel design of constant multiplications, shifts can be realized using only wires in hardware without representing any area cost a novel method has been proposed for the constant fir filter.For the shift-adds implementation of constant multiplications, a straightforward method, generally known as digit based recoding, initially defines the constants in binary. Then, for each "1" in the binary representation of the constant, according to its bit position, it shifts the variable and adds up the shifted variables to obtain the result. The digit-serial FIR filter designs obtained by SAFIR also indicate that the realization of the multiplier block of a digit-serial FIR filter under the shift adds architecture significantly reduces the area of digit-serial FIR filters with respect to those designed using digit-serial constant multipliers.

O autorze

Shashidhar, K.K.Shashidhar having more than 20 years of experience in the field of teaching. Completed Ph.D from GITAM University. M.Tech in VLSI System Design from JNTUH. Working as Associate professor in the department of ECE at GNITC, Hyderabad, affiliated to JNTUH. Worked in Malaysia affiliated to The Nottingham trend University UK for a period of 4 years.