Compressor on Multiplier Application

ISBN-13: 9786204752761 / Angielski / Miękka / 76 str.

RAJAT KUMAR DWIBEDI; HEMA L.K; PATTATHU RANI L

Opis

Multipliers are perhaps the main structure components in PC math, and they're commonly seen in digital signal processors. High-speed multipliers are in high demand in a variety of computing applications and some examples include computer graphics, scientific calculations, picture processing etcetera. The multiplier speed decides how rapidly the processors run, and designers are right now chipping away at fast with low power utilization. The three distinct stages in the multiplier design comprises of a partial product generator, a partial product reduction, and addition stage. Main stage which improves the overall multiplier performance is the reduction stage if there is a considerable change in this stage the overall multiplication delay, power, and area reduces drastically. Compressors are typically used to accumulate partial products since these add to the decrease just as the diminishing of the basic way, which is critical to keep up the circuit's exhibition.

O autorze

DWIBEDI, RAJAT KUMARMr. RAJAT KUMAR DWIBEDI obtained his Bachelor's Degree in Electronics and Communication Engineering from Institution of Engineers (India), Kolkata in the year 2001 and obtained Master's Degree in VLSI Design in the year 2009 from Sathyabama University, Chennai, India. He is currently pursuing Ph.D., in Vinayaka Missions Research Foundation (VMRF).