Co-Design for System Acceleration: A Quantitative Approach

ISBN-13: 9781402055454 / Angielski / Twarda / 2007 / 229 str.

Nadia Nedjah; Luiza De Macedo Mourelle; Luiza de Macedo Mourelle

Opis

This book is concerned with studying the co-design methodology in general, and how to determine the more suitable interface mechanism in a co-design system in particular. This is based on the characteristics of the application and those of the target architecture of the system. Guidelines are provided to support the designer's choice of the interface mechanism. Some new trends in co-design and system acceleration are also introduced.

Spis treści

List of Figures. List of Tables. Preface. Acknowledgment. Chapter 1: introduction. 1.1 synthesis. 1.2 design approaches. 1.3 co-design. 1.4 structure and objective. Chapter 2: co-design methodology. 2.1 the co-design approach. 2.2 system specification. 2.3 hardware/software partitioning. 2.4 hardware synthesis. 2.5 software compilation. 2.6 interface synthesis. 2.7 system integration. 2.8 summary. Chapter 3: The co-design system. 3.1 development route. 3.2 target architecture. 3.3 performance results. 3.4 summary. Chapter 4: VHDL modeling of a co-design system. 4.1 modelling with VHDL. 4.2 the main system. 4.3 the microcontroller. 4.4 the dynamic memory: DRAM. 4.5 the coprocessor. 4.6 summary. Chapter 5: shared memory configuration. 5.1 case study. 5.2 timing characteristics. 5.3 memory accesses and interface mechanisms. 5.4 summary. Chapter 6: dual-port memory configuration. 6.1 general description. 6.2 the system architecture. 6.3 timing characteristics. 6.4 performance results. 6.5 summary. Chapter 7: cache memory configuration. 7.1 memory hierarchy design. 7.2 system organization. 7.3 timing characteristics. 7.4 performance results. 7.5 summary. Chapter 8: advanced topics and further research. 8.1 conclusions and achievements. 8.2 advanced topics and further research. Appendices. A: benchmark programs. B: top-level VHDL model of the co-design system. C: translating PALASMtm2 into VHDL. D: VHDL version of the case study. References. Index.

Blurb

In Co-Design for System Acceleration, we are concerned with studying the co-design methodology, in general, and how to determine the more suitable interface mechanism in a co-design system, in particular. This will be based on the characteristics of the application and those of the target architecture of the system. We provide guidelines to support the designer's choice of the interface mechanism. The content of Co-Design for System Acceleration is divided into eight chapters. We present co-design as a methodology for the integrated design of systems implemented using both hardware and software components. This includes high-level synthesis and the new technologies available for its implementation. The physical co-design system is then presented. The development route adopted is discussed and the target architecture described. The relation between the execution times and the interface mechanisms is analyzed. In order to investigate the performance of the co-design system for different characteristics of the application and of the architecture, we developed a VHDL model of our co-design system. The timing characteristics of the system are introduced, that is times for parameter passing and bus arbitration for each interface mechanism, together with their handshake completion times. The relation between the coprocessor memory accesses and the interface mechanisms is then studied. Several memory configurations are presented and studied: single-port memory, dual-port memory and cache memory. We also introduce some new trends in co-design and system acceleration.