1. Brief introduction CMOS applications in our daily life 2. Basic definitions and equations 3. Electrical measurements (IV, short channel effects, mobility and noise) 4. CMOS Architecture 5. Strain engineering (stressor materials in source/drain regions, strain induced by processing, stress liners) 6. High-k and metal gate (Almost all known high-k materials and metal gates) 7. Channel materials (Ge, GeSn, SiGe, Graphene and other II-D crystals, III-V compounds) 8. Contacts (Silicide formation, contact resistance, parasitic contacts) 9. Integration with photonic components (CMOS with lasers, detectors) 10. Technology roadmap (starting from 50's to unknown future) 11. Authors' final words
Henry H. Radamson received an M.Sc. degree in physics and the Ph.D. degree in semiconductor materials from Linköping University in Sweden, in 1989 and 1996, respectively. In 1997, he joined the Royal Institute of Technology in Stockholm as a senior scientist, where he has been an Associate Professor since 2001.
Eddy Simoen is a Senior Researcher at IMEC, where he is currently involved in research on the defect and strain engineering in high-mobility and epitaxial substrates and defect studies in germanium and III-V compounds.
Dr. Jun Luo joined the Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, China in August, 2010. His current research interests cover the CMOS technology, Si/SiGe devices and process technology, energy harvesting devices based on Si technology and GaN-on-Si HEMTs.
Dr. Zhao is a research professor and the Director of Integrated Circuit Advanced Process Center of IMECAS (Institute of Microelectronics of Chinese Academy of Science). In 1982, he graduated from Physics Department of Nanjing University in China with a Bachelor Degree. He received a master degree from University of Industry of Harbin in Semiconductor in 1988 and a PHD degree from Katholieke University of Leuven in Belgium in 1999. Between 2000 and 2010, he was working as a senior scientist in IMEC and took part in IMEC IIAP program on High-k, Cu connection, Cu contact and TSV 3D IC. His research experience and interest covers both FEOL and BEOL processing technologies in 8-inch and 12 inch pilot lines. He has authored and co-authored 130 scientific papers and has filed more than 80 invention patents in IC processing technology.