CAD for Hardware Security

ISBN-13: 9783031268953 / Angielski

Farimah Farahmandi; M. Sazadur Rahman; Sree Ranjani Rajendran

Opis

This book provides an overview of current hardware security problems and highlights how these issues can be efficiently addressed using computer-aided design (CAD) tools. Authors are from CAD developers, IP developers, SOC designers as well as SoC verification experts. Readers will gain a comprehensive understanding of SoC security vulnerabilities and how to overcome them, through an efficient combination of proactive countermeasures and a wide variety of CAD solutions.

Spis treści

Introduction.- CAD for Information Leakage Assessment.- CAD for Power Side Channel Leakage Assessment.- CAD for Electromagnetic Radiation Leakage Assessment.- CAD for Timing Leakage Assessment.- CAD for Fault Injection Attack Analysis.- CAD for Obfuscation.- CAD for Watermarking.- CAD for HW Metering.- CAD for Detecting HLS Vulnerabilities.- CAD for Counterfeit Detection and Prevention.- CAD for Trojan Detection and Prevention.- CAD for Physical Assurance.- CAD for Anti-Probing.- CAD for Formal Security Verification.- CAD for Reverse Engineering.

O autorze

Farimah Farahmandi is an assistant professor in the Department of Electrical and Computer Engineering (ECE) and the associate director of Edaptive Computing Inc., Transition Center (ECI-TC), and Florida Institue for Cybersecurity (FICS) at the University of Florida. She received her Ph.D. from the Department of Computer and Information Science and Engineering (CISE) at the University of Florida, 2018. Her research interests include hardware security verification, formal methods, fault-injection attack analysis, side-channel leakage assessment, information leakage, secure physical design, secure supply chain of microelectronics, and post-silicon validation and debug. Her research has resulted in five books, nine book chapters, and several publications in premier ACM/IEEE journals and conferences including IEEE Transactions on Computers, IEEE Transactions on CAD, Design Automation Conference (DAC), and Design Automation and Test in Europe (DATE). Her research has been recognized by several awards including 2022 Semiconductor Research Corporation Young Faculty Award and the 2022 ECE Research Excellence Award at UF. She is also the recipient of four best paper nominations from IEEE/ACM ASPDAC and IEEE/ACM DATE as well as IEEE System Validation and Debug Technology Committee Student Research Award, Gartner Group Info-Tech Scholarship, and DAC Richard Newton Young Student Fellowship. She currently serves as an Associate Editor of IET Computers & Digital Techniques. She also has served on many technical program committees as well as organizing committees of premier ACM and IEEE conferences. Currently, she is the program chair of IEEE HOST 2023. Her research has been sponsored by SRC, DARPA, AFRL, DoD, ONR, Analog Devices, ANSYS, Synopsys, and Cisco. She is a member of IEEE and ACM.

M Sazadur Rahman a Security Assurance architecture Engineer at Intel Corporation. He earned his M.Sc. and Ph.D. degree under the supervision of Prof. Mark Tehranipoor from University of Florida in 2022. He got his B.Sc. in Electrical and Electronic Engineering from the Bangladesh University of Engineering and Technology in 2014. He worked as a design engineer in different fabless semiconductor companies from 2014 to 2017 in industrial scale 28nm and 14nm custom ICs. His research has resulted in one book, multiple patents, and several peer-reviewed publications in premier ACM/IEEE journals and conferences, including the Design Automation Conference (DAC), Design automation and test in Europe (DATE), IEEE International Test Conference (ITC), IEEE Hardware Oriented Security and Trust (HOST), IEEE VLSI Test symposium (VTS), Elsevier Integration, ACM Transactions on Design Automation of Electronic Systems (TODAES), etc. He has multiple internship experiences at Intel Corporation, where he performed FIPS 140-3 security certification and developed an automated threat model review tool for different adversary models. His research interest includes IP protection and authentication, logic locking, security estimation, and CAD for security.

Sree Ranjani Rajendran is a postdoctoral associate in the Department of Electrical and Computer Engineering at the University of Florida. She received her Ph.D. from the Department of Electronics and Communication Engineering at the Amrita Vishwa Vidyapeetham in 2019. She received her B.E. and M.E. from the Department of Electronics and Communication Engineering at Anna University, sIndia, in 2007 and 2012.Her research interests include hardware security verification and validation of System-on-Chips.  Her research has been published in premier ACM/IEEE journals and conferences, including IEEE Transactions on Emerging Topics in Computing, Journal of Cryptographic Engineering, ACM Workshop on Attacks and Solutions in Hardware Security, International Conference on VLSI Design & The International Conference on Embedded Design, and Design Automation and Test in Europe (DATE). She is a member of IEEE and The Test Technology Technical Community (TTTC). Her research has been awarded in IEEE Young Women Research Grant Award, 28th IEEE Asian Test Symposium (ATS), 2019. 

Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity and the Chair of the Department of Electrical and Computer Engineering (ECE) at the the University of Florida. He served as the founding Director for Florida Institute for Cybersecurity (FICS) Research from 2015-2022, and currently serving as Director for Edaptive Computing Inc. Transition Center (ECI-TC), Co-director for the AFOSR/AFRL Center of Excellence on Enabling Cyber Defense in Analog and Mixed Signal Domain (CYAN), and Co-Director for the National Microelectronic Security Training Center (MEST). He also served as the Associate Chair for Research and Strategic Initiatives for the ECE Department from 2017-2019 and the Program Director of Cybersecurity in the Herbert Wertheim College of Engineering from 2019-2022. His current research projects include hardware security and trust, electronics supply chain security, IoT security, and reliable and testable VLSI design. Dr. Tehranipoor has published numerous journal articles and refereed conference papers and has delivered 220+ invited talks and keynote addresses. In addition, he has 19 patents issued, 22 pending invention disclosures, and has published 16 books of which two are textbooks. His projects have been sponsored by 50+ companies and Government agencies. Dr. Tehranipoor is a Fellow of IEEE, a Fellow of ACM, a Fellow of the National Academy of Engineering (NAI), a Golden Core Member of IEEE Computer Society, and a Member of ACM SIGDA. He is also a member of the Connecticut Academy of Sciences and Engineering (CASE). He is a recipient of 17 best paper awards and nominations, the 2009 NSF CAREER award, the 2014 AFOSR MURI award on Nanoscale Security, the 2008 IEEE Computer Society (CS) Meritorious Service award, the 2012 and 2017 IEEE CS Outstanding Contribution, the 2010 and 2016 IEEE TTTC/CS Most Successful Technical Event for co-founding and chairing HOST Symposium, the 2018 IEEE HOST Hall of Fame Member, the 2009 and 2014 UConn ECE Research Excellence award, the 2012 UConn SOE Outstanding Faculty Advisor award, the 2016 UF College of Engineering Excellence in Leadership award, the 2016 UF ECE Research Excellence Award, the 2020 UF’s College of Engineering Teacher/Scholar of the year award, the 2020 UF Innovation of the Year Award, and the 2022 IEEE CS TTTC Bob Madge Innovation Award. He serves on the program committee of more than a dozen leading conferences and workshops. Prof. Tehranipoor served as the guest editor for JETTA, IEEE Design and Test of Computers, ACM JETC, and IEEE Computer Society Computing Now. He served as Program Chair of the 2019 International Test Conference (ITC), Vice-program Chair of the 2018 ITC, Program Chair of the 2007 IEEE Defect-Based Testing (DBT) workshop, 2016 IEEE International Verification and Security Workshop (IVSW), Program Chair of the 2008 IEEE Defect and Data Driven Testing (D3T) workshop, Co-program Chair of the 2008 International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), General Chair for D3T-2009 and DFTS-2009, and Vice-general Chair for NATW-2011, General Chair for 2008-2009, and 2021-2022 IEEE HOST, and General Chair for 2019-2021 IEEE PAINE Conference. Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut.

Blurb

This book provides an overview of current hardware security problems and highlights how these issues can be efficiently addressed using computer-aided design (CAD) tools. Authors are from CAD developers, IP developers, SOC designers as well as SoC verification experts. Readers will gain a comprehensive understanding of SoC security vulnerabilities and how to overcome them, through an efficient combination of proactive countermeasures and a wide variety of CAD solutions.

• Offers techniques to protect hardware designs from a variety of vulnerabilities using CAD;
• Provides a comprehensive introduction to current SoC security vulnerabilities at different levels of abstraction;
• Discusses CAD-based approaches and their application to SoC security issues at various levels of design abstraction.