Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures

ISBN-13: 9783030797768 / Angielski / Miękka / 2022 / 232 str.

Mark Wijtvliet;Henk Corporaal;Akash Kumar

Opis

This book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs. The book starts with an extensive evaluation of historic and existing CGRAs and their strengths and weaknesses. This also leads to a better understanding and new definition of what distinguishes CGRAs from other architectural approaches. The authors introduce Blocks as unique due to its separate programmable control and data paths, allowing light-weight instruction decode units to be arbitrarily connected to one or more functional units (FUs) over a statically configured interconnect. The discussion includes an explanation of how to model architectures, resulting in an area and energy model for Blocks. The accuracy of this model is evaluated against fully implemented architectures, showing that although it is three orders of magnitude faster than synthesis the error margin is very acceptable. The book concludes with a case study on a real System-on-Chip, including a RISC architecture, the Blocks CGRA and peripherals.

Spis treści

1) Introduction

2) CGRA background and related work

3) Concept of the Blocks architecture

4) The Blocks framework

5) Energy, area, and performance evaluation

6) Architectural model

7) Case study: the BrainSense platform

8) Conclusions and future work

O autorze

Mark Wijtvliet is a postdoctoral researcher at Dresden University of Technology. He received his Ph.D. degree from Einhdoven University in 2020 and the MSc degree from Eindhoven University of Technology, in the field of Electrical Engineering, in 2011. He worked for two years on a combined project between Eindhoven University of Technology and Delft University of Technology researching algorithmic skeletons on FPGA implementations. This research led to the inspiration of the Blocks reconfigurable architecture. From 2014 he continued working as a researcher at Eindhoven University of Technology and started his PhD research in 2014 in the Electronic Systems group within the rCPS P3 project. During this time, he also was the project leader for the PR3 student team that built a payload to fly on a sounding rocket and participated in the HiPEAC exchange program at the CFAED group at Dresden University of technology. Mark was also involved in organization and teaching of the courses Embedded Computer Architecture (in which Blocks was used by many students) and Embedded Visual Control. His interests include energy-efficient reconfigurable architectures, robotics, and space applications. He is currently working as a postdoc for the CFAED group at TU Dresden.

Henk Corporaal is Professor in Embedded System Architectures at the Einhoven University of Technology (TU/e) in The Netherlands. He has gained a MSc in Theoretical Physics from the University of Groningen, and a PhD in Electrical Engineering, in the area of Computer Architecture, from Delft University of Technology. 

Corporaal has co-authored over 500 journal and conference papers. Furthermore, he invented a new class of VLIW architectures, the Transport Triggered Architectures, which is used in several commercial products, and by many research groups.

His research is on low power multi-processor, heterogenous processing architectures, their programmability, and the predictable design of soft- and hard real-time systems. This includes research and design of embedded system architectures, including CGRAs, SIMD, VLIW and GPUs, on accelerators, the exploitation of all kinds of parallelism, fault-tolerance, approximate computing, architectures for machine and deep learning, optimizations and mapping of deep learning networks, and the (semi-)automated mapping of applications to these architectures. Publications can be found at Google Scholar. For further details, see corporaal.org.

Akash Kumar is a chaired Professor of Processor Design (with tenure) in the department of Computer Science at Technische Universität Dresden (TUD), Germany. From 2009 to 2015, he was with the Department of Electrical and Computer Engineering, NUS. He received the joint Ph.D. degree in electrical engineering in embedded systems from Eindhoven University of Technology (TU/e) and National University of Singapore (NUS), in 2009; joint Master’s degree from TU/e and NUS in 2005 in embedded systems and Bachelor of Computer Engineering degree from NUS in 2002.

His research interests span various aspects of design automation in the context of embedded real-time systems with particular emphasis on reliable, resource-efficient and predictable architectures for embedded systems, including FPGA-based architectures. His research spans across various layers in the system design from hardware design to application analysis. He has published close to 170 articles in premier international conferences and journals in the area of design automation. Together with his research group, he has released many open-source tool flows for system design and analysis to allow the community to reproduce their results and to further research in the related areas.

He serves (or has recently served) on the program committee of renowned conferences in the area like DAC, DATE, FPL and CASES. He was the program chair of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’18 and ’19), Embedded Systems for Real-Time Multimedia (ESTIMedia ’17), subcommittee chair for several editions of Design Automation and Test in Europe (DATE) conference and Brief Presentations Chair for Real-time Systems Symposium (RTSS’19) and Associate Editor for Elsevier Microprocessors and Microsystems journal for 2013-2017 and ACM Transactions on Embedded Computing Systems (TECS) special issue. He is currently an associate editor for IEEE Embedded Systems Letters (ESL) and MDPI Electronics.

He has received Best Paper Award at DATA 2018, and best paper award nominations at DATE 2015, 2017 and 2020, FPL 2014, GLSVLSI 2014, ISVLSI 2020 and Supercomputing Conference 2015. His group also received HiPEAC Technology transfer award 2019. His current publication and citation profile can be found at Google scholar. According to CS-rankings, he is one of the most published Professor in top conferences at TU Dresden in Computer Science.

Blurb

This book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs. The book starts with an extensive evaluation of historic and existing CGRAs and their strengths and weaknesses. This also leads to a better understanding and new definition of what distinguishes CGRAs from other architectural approaches.

The authors introduce Blocks as unique due to its separate programmable control and data paths, allowing light-weight instruction decode units to be arbitrarily connected to one or more functional units (FUs) over a statically configured interconnect. The discussion includes an explanation of how to model architectures, resulting in an area and energy model for Blocks. The accuracy of this model is evaluated against fully implemented architectures, showing that although it is three orders of magnitude faster than synthesis the error margin is very acceptable. The book concludes with a case study on a real System-on-Chip, including a RISC architecture, the Blocks CGRA and peripherals.

• Provides a comprehensive overview of many coarse-grained reconfigurable architectures (CGRAs) proposed in the last 25 years, as well as a classification of those CGRAs;
• Offers a new view on the positioning of CGRAs;
• Provides an in-depth description of structure of the Blocks CGRA and its unique aspects;
• Includes an extensive evaluation of various performance aspects of Blocks, such as performance, energy and area, as well as a comparison with various traditional approaches;
• Uses a case study showing how Blocks can be used in a real system on-chip, and how performance of this system-on-chip can be estimated using the proposed model.