Analysis of DRAM Cell Designs for Nanometer-Scale Memories

ISBN-13: 9786202557405 / Angielski / Miękka / 2020 / 80 str.

Prateek Asthana

Opis

This book is aimed at improving the power consumption and timing parameter for Dynamic Random Access Memory cells which are used in the construction of the main memory cell. DRAM is widely used for main memories in personal and mainframe computers and engineering workstations. DRAM memory cell is used for reading and write operation for single bit storage for circuits. A single DRAM cell is capable of storing 1bit data in the capacitor in the form of charge. In this book, three different DRAM memory cells are constructed on TANNER EDA, their simulation is carried out. Average power consumption, read access time, write access time and retention time values are calculated for all the three SDRAM cells. The three DRAM cells used are 4T, 3T, and 3T1D DRAM memory cells. Average power consumption, read access time, write access time and retention time-values are calculated at varying supply voltages. To improve the average power consumption, read access time, write access time, and retention time of the 3T1D DRAM memory cell techniques are applied. After the application of techniques on the circuit design, all the parameter values are again calculated and compared with existing value.

O autorze

Asthana, Prateek
Prateek Asthana - University researcher at the National Institute of Technology (NIT) Hamirpur. He completed his masters at JSS Academy in the field of DRAM Memory Design. He has 6 papers in international reputed journals&over 10 papers in national and international conferences. His current area of research include VLSI and MEMS Energy harvesting.