An Artificial Intelligence Approach to VLSI Routing

ISBN-13: 9780898382051 / Angielski / Twarda / 1985 / 160 str.

Rostam Joobbani; R. Joobbani

Opis

Routing of VLSI chips is an important, time consuming, and difficult problem. The difficulty of the problem is attributed to the large number of often conflicting factors that affect the routing quality. Traditional techniques have approached routing by ignoring some of these factors and imposing unnecessary constraints in order to make routing tractable. In addition to the imposition of these restrictions, which simplify the problems to a degree but at the same time reduce the routing quality, traditional approaches use brute force. They often transform the problem into mathematical or graph problems and completely ignore the specific knowledge about the routing task that can greatly help the solution. This thesis overcomes some of the above problems and presents a system that performs routing close to what human designers do. In other words it heavily capitalizes on the knowledge of human expertise in this area, it does not impose unnecessary constraints, it considers all the different factors that affect the routing quality, and most importantly it allows constant user interaction throughout the routing process. To achieve the above, this thesis presents background about some representative techniques for routing and summarizes their characteristics. It then studies in detail the different factors (such as minimum area, number of vias, wire length, etc.) that affect the routing quality, and the different criteria (such as vertical/horizontal constraint graph, merging, minimal rectilinear Steiner tree, etc.) that can be used to optimize these factors.

Spis treści

1. Introduction.- 1.1. Motivation.- 1.2. Outline.- 2. Detailed Routing.- 2.1. Problem Statement.- 2.2. Important Factors in Routing.- 2.3. Previous Approaches.- 2.3.1. Lee Algorithm.- 2.3.2. Line Routing Algorithms.- 2.3.3. Efficient Algorithms for Channel Routing.- 2.3.4. A “Greedy” Channel Router.- 2.3.5. Hierarchical Wire Routing.- 2.4. Characteristics of Previous Approaches.- 3. WEAVER Approach.- 3.1. Congestion.- 3.2. Wire Length.- 3.3. Rectilinear Steiner Tree.- 3.3.1. Steiner Tree.- 3.3.2. Minimal Rectilinear Steiner Tree for a 2xn Grid.- 3.3.3. Minimal Rectilinear Steiner Tree for A mxn Grid.- 3.4. Merging.- 3.5. Vertical/Horizontal Constraint Graph.- 3.6. Intersection.- 3.7. Conflicting Effects.- 4. Knowledge-Based Expert Systems.- 4.1. Productions Systems.- 4.2. OPS5.- 4.2.1. Working Memory.- 4.2.2. Production Memory.- 4.2.3. Interpreter.- 4.3. Applicability of Knowledge-Based Expert Systems to VLSI Design.- 4.3.1. Detailed Routing of VLSI Chips is Amenable to the Techniques of Applied AI.- 4.3.2. Detailed Routing of VLSI Chips is Important, Difficult and a High-Value Problem.- 4.4. Advantages and Disadvantages of Knowledge-Based Expert Systems.- 5. WEAVER Implementation.- 5.1. Problem State Representation.- 5.2. WEAVER Architecture.- 5.3. Blackboard Organization.- 5.4. WEAVER Experts.- 5.4.1. Wire Length Expert.- 5.4.2. Merging Expert.- 5.4.3. Congestion Expert.- 5.4.4. Vertical/Horizontal Constraint Expert.- 5.4.5. Via Expert.- 5.4.6. Common Sense Expert.- 5.4.7. Pattern Router Expert.- 5.4.8. Constraint Propagation Expert.- 5.4.9. User Expert.- 5.4.10. Minimal Rectilinear Steiner Tree Expert.- 5.5. WEAVER Control Structure.- 5.5.1. Nature of WEAVER Expertise.- 5.5.2. Generality of WEAVER Knowledge.- 5.6. Program Organization.- 6. Experiments and Results.- 6.1. Input/Output.- 6.1.1. Input.- 6.1.2. Output.- 6.2. Step by Step Trace of Routing a Channel.- 6.3. Experiments.- 6.3.1. Comparison with Efficient Algorithms for Channel Routing.- 6.3.2. Comparison with the Greedy Algorithm When Both can Route the Channel.- 6.3.3. WEAVER’s Routing of a Channel Unroutable by the Greedy Algorithm.- 6.3.4. WEAVER’s Solution to Provably Unroutable Channel and Switch-Box by Traditional Algorithms.- 6.3.5. Comparison with Aker’s and Lee Algorithms.- 6.3.6. Comparison with the Minimum-Impact Routing Algorithm.- 6.3.7. Burstein’s Difficult Switch-Box.- 6.3.8. Terminal Intensive Example.- 6.3.9. Dense Switch-Box Example.- 6.3.10. Conclusion to the Experiments.- 6.4. WEAVER’s Performance Under Conditions of Disabled Experts.- 6.4.1. Merging Expert Disabled.- 6.4.2. Congestion and Merging Experts Disabled.- 6.4.3. Via Expert Disabled.- 6.4.4. Vertical/Horizontal Constraint Expert Partially Disabled.- 6.4.5. Rectilinear Steiner Tree Expert Disabled.- 6.4.6. Summary of the Results of Disabling the Experts.- 6.5. Efficiency Issues.- 6.5.1. Possible Execution Time Improvement.- 6.5.2. Writing Efficient OPS5 Programs.- 7. Conclusions and Future Work.- References.