Advances in Embedded and Fan-Out Wafer Level Packaging Technologies

ISBN-13: 9781119314134 / Angielski / Twarda / 2019 / 576 str.

Beth Keser; Steffen Kroehnert

Spis treści

Preface xviiList of Contributors xxiiiAcknowledgments xxvii1 History of Embedded and Fan-Out Packaging Technology 1Michael Topper, Andreas Ostmann, Tanja Braun, and Klaus-Dieter Lang2 FO-WLP Market and Technology Trends 39E. Jan Vardaman3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform 55Thorsten Meyer and Steffen Krohnert4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology 77S.W. Yoon5 NEPES' Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging 97Jong Heon (Jay) Kim6 M-Series Fan-Out with Adaptive Patterning 117Tim Olson and Chris Scanlan7 SWIFTR Semiconductor Packaging Technology 141Ron Huemoeller and Curtis Zwenger8 Embedded Silicon Fan-Out (eSiFOR) Technology for Wafer-Level System Integration 169Daquan Yu9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology 185Thomas Gottwald, Christian Roessle, and Alexander Neumann10 Embedding of Power Electronic Components: The Smart p2 Pack Technology 201Thomas Gottwald and Christian Roessle11 Embedded Die in Substrate (Panel-Level) Packaging Technology 217Tomoko Takahashi and Akio Katsumata12 Blade: A Chip-First Embedded Technology for Power Packaging 241Boris Plikat and Thorsten Scharf13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology 261Katsushi Kan, Michiyasu Sugahara, and Markus Cichon14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP) 271T. Enomoto, J.I. Matthews, and T. Motobe15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer-Level Packaging 317Stefan Vanclooster and Dimitri Janssen16 The Role of Pick and Place in Fan-Out Wafer-Level Packaging 347Hugo Pristauz, Alastair Attard, and Harald Meixner17 Process and Equipment for eWLB: Chip Embedding by Molding 371Edward Furgut, Hirohito Oshimori, and Hiroaki Yamagishi18 Tools for Fan-Out Wafer-Level Package Processing 403Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung19 Equipment and Process for eWLB: Required PVD/Sputter Solutions 419Chris Jones, Ricardo Gaio, and Jose Castro20 Excimer Laser Ablation for the Patterning of Ultra-fine Routings 441Habib Hichri, Markus Arendt, and Seongkuk Lee21 Temporary Carrier Technologies for eWLB and RDL-First Fan-Out Wafer-Level Packages 457Thomas Uhrmann and Boris Pova?ay22 Encapsulated Wafer-Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection 471S.W. Yoon23 Embedded Multi-die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect 487Ravi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems 501Paragkumar A. Thadesar, Paul K. Jo, and Muhannad S. BakirReferences 515Index 521

O autorze

Beth Keser, Ph.D., is a recognized global leader in the semiconductor industry with over 20 years' experience resulting in 28 patents and patents pending and over 40 publications. She is an IEEE Senior Member whose volunteer activities and professional society responsibilities include: IEEE EPS' VP of Education, 2015 ECTC General Chair, and more.Steffen Kröhnert, M.SC., is Senior Director of Technology Development at Amkor Technology Holding B.V., Germany. He has more than 20 years' experience in the semiconductor industry. Steffen is author and co-author of 23 patent filings in the area of Semiconductor Packaging Technology, and an active member of IEEE EPS, IMAPS, SMTA, VDI, VDE and GPM.