ASIC Implementation of Pezaris Multiplier in DIT FFT Architectures

ISBN-13: 9786139900619 / Angielski / Miękka / 2018 / 52 str.

Saranya Karunamurthi; Vinoth Kumar Bojan; Baby Janagam Ramachandran

Opis

Multipliers with large bit lengths have a major impact on the performance of digital circuits in many applications like cryptography, digital signal processing and image processing. The performances of many computational problems are often dominated by the speed at which a multiplication operation can be executed. This book gives a brief overview of various multipliers such as Baugh Wooley, Pezaris, Array, Booth, Vedic multipliers and Compressor based multipliers. The main objective is to compare various types of multiplier in terms of power consumption, area and delay. These signed multiplication concepts are implemented in Verilog HDL and implemented in Cadence RTL Compiler with 180nm technology.

O autorze

Karunamurthi, SaranyaMrs. Saranya Karunamurthi is working as an Assistant Professor, Department of EEE in Dr. Mahalingam College of Engineering & Technology, Pollachi, Tamil Nadu, India. She completed her Master Degree in Applied Electronics under Anna University. Her research interests are VLSI Design, Analog & Digital Circuits, Reversible logics, ASIC Implementation.