A One-Semester Course in Modeling of VSLI Interconnections

ISBN-13: 9781606505120 / Angielski / Miękka / 2014 / 180 str.

Ashok Goel

Opis

Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits.The optimum design of state-of-the-art integrated circuits relies heavily on quantitative understanding of the parasitic capacitances and inductances in the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrate circuits (VSLI). This is because more than 65% of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Modeling of VSLI Interconnections will discuss the mathematical techniques necessary to model the parasitic capacitances, inductances, propagation delays, crosstalk noise and electro migration-induced failure associated with the interconnections in the realistic high-density environment on a chip. This book will be the first of its kind written for a one-semester course on the mathematical modeling of metallic interconnections on a VLSI circuit. In most institutions around the world, this course will be offered at an upper-level undergraduate and beginning graduate level. The book will also be of interest to practicing engineers in the field who are looking for a quick refresher on the subject.

Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. More than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. A One-Semester Course in Modeling of VLSI Interconnections also includes an overview of the future interconnection technologies for the nanotechnology circuits.