A High Performance Architecture for PROLOG

ISBN-13: 9781461288206 / Angielski / Miękka / 2013 / 218 str.

T. P. Dobry

Opis

Artificial Intelligence is entering the mainstream of com- puter applications and as techniques are developed and integrated into a wide variety of areas they are beginning to tax the pro- cessing power of conventional architectures. To meet this demand, specialized architectures providing support for the unique features of symbolic processing languages are emerging. The goal of the research presented here is to show that an archi- tecture specialized for Prolog can achieve a ten-fold improve- ment in performance over conventional, general-purpose architec- tures. This book presents such an architecture for high perfor- mance execution of Prolog programs. The architecture is based on the abstract machine descrip- tion introduced by David H.D. Warren known as the Warren Abstract Machine (W AM). The execution model of the W AM is described and extended to provide a complete Instruction Set Architecture (lSA) for Prolog known as the PLM. This ISA is then realized in a microarchitecture and finally in a hardware design. The work described here represents one of the first efforts to implement the W AM model in hardware. The approach taken is that of direct implementation of the high level WAM instruction set in hardware resulting in a elSe style archi- tecture.

Spis treści

1 Introduction.- Logic Programming.- A Prolog Model.- Some Example Applications in Prolog..- Progress in Prolog Implementations..- Computer Architecture.- Other Symbolic Computing Processors.- The Japanese PSI..- The LISP Machines..- The SPUR Project..- Motivation.- Contributions.- Organization.- 2 An Abstract Prolog Machine.- Data Types.- Memory Areas.- Some Definitions.- Instruction Set.- Procedure Code..- Indexing Code..- Clause Code..- Data Manipulation Code..- An Example of Compiled Code..- Fundamental Operations.- Failure..- Variable Binding and Dereferencing..- Trailing..- General Unification..- Summary.- 3 A Modified WAM.- Address Space of the PLM.- Representing Data..- Representing Code..- Completing the Instruction Set.- Support for cdr-coding..- The cut Operation..- An Unnecessary Instruction..- Enhancements to the WAM.- The Environment Size..- Indexing Instructions..- An Unnecessary Register..- Tail Recursion Revisited..- Implementing Built-in Functions.- Compiler Implemented Built-ins..- Internal Built-ins..- External Built-ins..- Some Particularly Difficult Built-ins..- Side-effect Variables..- General assert and retract — Overview..- Code Space Modification..- Summary.- 4 The Architecture Becomes a Machine.- The Prefetch Unit.- Defining a Basic Data Path.- Defining a Microengine.- Tuning the Data Path and the Microcode.- The Path to Memory.- Write Buffering..- Choice Point Cache..- Environment and Trail Buffering..- Summary.- 5 The Experiment.- Methodology.- The Simulators.- ISA Simulation — Level 1..- RTL Simulation — Level 2..- The Benchmark Set.- Results.- Determinate concat — A Case Study..- The Effects of cdr-coding..- The Effects of Environment Trimming..- The Effects of Sidetracking..- The Effects of Host and Memory Speed..- The Effects of Buffers and Caches..- A Critique of the PLM Microcode..- Further Improvements to the PLM.- Summary.- 6 Conclusions.- Directions for Future Research.- Conclusions.