Computer Architecture: A Quantitative Approach

ISBN-13: 9780128119051 / Angielski / Miękka / 2017 / 936 str.

Un Emeritus David A. (Pardee Professor of Computer Science

Opis

For over 20 years, Computer Architecture: A Quantitative Approach has been considered essential reading by instructors, students, and practitioners of computer design. The latest edition of this classic textbook is fully revised with the latest developments in processor and system architecture. It now features examples from the RISC-V ("RISC Five") instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC. True to its original mission of demystifying computer architecture, the sixth edition of Computer Architecture: A Quantitative Approach continues its longstanding tradition of focusing on the areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design.

• Includes a new chapter on domain-specific architectures, explaining how they are only path forward for improved performance and energy efficiency given the end of Moore's Law and Dinnard scaling. Features first publication of several DSAs from industry
• Features extensive updates to the chapter on warehouse-scale computing, with first public information on the newest Google WSC
• Updates to other chapters include new material dealing with the use of stacked DRAM; data on the performance of new Nvidia Pascal GPU vs new AVX/512 Intel Skylake CPU; and extensive additions to content covering multicore architecture and organization
• Trademark Putting It All Together sections appear near the end of every chapter, providing real-world technology examples that demonstrated the principles covered in each chapter
• Includes review appendices in the printed text and additional reference appendices available online
• Includes updated and improved case studies and exercises

Recenzje

"What has made this book an enduring classic is that each edition is not an update, but an extensive revision that presents the most current information and unparalleled insight into this fascinating and fast changing field. For me, after over twenty years in this profession, it is also another opportunity to experience that student-grade admiration for two remarkable teachers." --From the Foreword by Luiz Andre Barroso, Google, Inc.

Spis treści

Printed Text 1. Fundamentals of Quantitative Design and Analysis 2. Memory Hierarchy Design 3. Instruction-Level Parallelism and Its Exploitation 4. Data-Level Parallelism in Vector, SIMD, and GPU Architectures 5. Multiprocessors and Thread-Level Parallelism 6. The Warehouse-Scale Computer 7. Domain Specific Architectures A. Instruction Set Principles B. Review of Memory Hierarchy C. Pipelining: Basic and Intermediate Concepts

Online D. Storage Systems E. Embedded Systems F. Interconnection Networks G. Vector Processors H. Hardware and Software for VLIW and EPIC I. Large-Scale Multiprocessors and Scientific Applications J. Computer Arithmetic K. Survey of Instruction Set Architectures L. Advanced Concepts on Address Translation M. Historical Perspectives and References

O autorze

ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. John L. Hennessy is a Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a member of the faculty since 1977 and was, from 2000 to 2016, its tenth President. Prof. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neumann Award, which he shared with David Patterson. He has also received seven honorary doctorates. David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1977.His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Prof. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Prof. Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH.