ISBN-13: 9780128112557 / Angielski / Miękka / 2017 / 190 str.
Resource Efficient LDPC Decoders: From Algorithms to Hardware Architectures takes a practical hands-on approach to developing low complexity algorithms and how to transform them into working hardware. It follows a complete design approach, from algorithms to hardware architectures, and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. Readers will learn modern techniques to design, model and analyze low complexity LDPC algorithms, along with tactics on their hardware implementation, how to reduce computational complexity and power consumption using computer-aided design techniques, and all aspects of the design spectrum, from algorithms to hardware implementation and performance tradeoffs.