Resource Efficient Ldpc Decoders: From Algorithms to Hardware Architectures

ISBN-13: 9780128112557 / Angielski / Miękka / 2017 / 190 str.

Sayed Mahfuzul Aziz; Vikram A. Chandrasetty

Opis

Resource Efficient LDPC Decoders: From Algorithms to Hardware Architectures takes a practical hands-on approach to developing low complexity algorithms and how to transform them into working hardware. It follows a complete design approach, from algorithms to hardware architectures, and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. Readers will learn modern techniques to design, model and analyze low complexity LDPC algorithms, along with tactics on their hardware implementation, how to reduce computational complexity and power consumption using computer-aided design techniques, and all aspects of the design spectrum, from algorithms to hardware implementation and performance tradeoffs.

• Provides extensive treatment of LDPC decoding algorithms and hardware implementations
• Presents systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms
• Addresses some of the challenges associated with design, providing insight into implementing innovative architectures

Spis treści

1. Introduction2. Overview of LDPC codes3. Structure and flexibility of LDPC codes4. LDPC decoding algorithms5. LDPC decoder architectures6. Hardware implementation of LDPC decoder7. LDPC decoders in multimedia communication8. Prospective LDPC applications

AppendixA : Sample C-Programs and MATLAB models for LDPC code construction and simulationB : Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architectureC : Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture