Realization of Memory Fault Tolerance using Error Correcting Codes

ISBN-13: 9783330044197 / Angielski / Miękka / 2017 / 128 str.

N. S. Murti Sarma; Poluboyina Lavanya; Gobinda Prasad Acharya

Opis

This work is aimed towards the implementation of a fault-tolerant memory system with the help of supporting circuits. This work demonstrates an improvement on the reliability of a semiconductor memory system using Error control codes (ECC)and Low Density Parity Check (LDPC) Codes as a part of protecting support logic. It is observed that the error correcting codes with higher hamming distances can detect more errors i.e. as higher the hamming distance higher the error control capability.

O autorze

Asst.Prof.Poluboyina Lavanya and Assoc.Prof.Gobinda Prasad Acharya are upgrowing research scholars of JNTUK and JNTUH in the areas of wireless networks and VLSI testing respectively. N S Murti Sarma together with above are faculty of Sreenidhi Institute of Science and Technology. All the authors of the book are with significant credits of research.