SATH: Simulated Annealing C code To FPGA Hardware compiler : Customizing Pipelined Simulated Annealing IP cores with a dedicated C to FPGA compiler

ISBN-13: 9783639165128 / Angielski / Miękka / 2009 / 132 str.

Jonathan Phillips

Opis

A tool flow is presented for deriving acceleratorcircuits on an FPGA from ANSI C source code by exploring architecturesolutions that conform to a preset template through scheduling andmapping algorithms. A case study carried out on simulatedannealing-based scheduling software used for spacecraft systems isexplained. The goal of the tool is the derivation of a design thatmaximizes throughput while minimizing footprint. Results obtained arecompared with a peer C to RTL tool, a space-borne embedded processor and acommoditydesktop processor for a variety of problems.

O autorze

Dr. Jonathan Phillips received his B.S. (Brigham Young
University, 2000), his M.S. and
Ph.D. in Electrical Engineering (Utah State University, 2004 and
2008). He is currently
employed at the USU Research Foundation, where he continues to
investigate real-
world applications for multi-FPGA data processing and
communications systems.