Output-Capacitor-Free Low-Dropout Regulators: Analysis and Design » książka
Output-Capacitor-Free Low-Dropout Regulators: Analysis and Design
ISBN-13: 9783659291883 / Angielski / Miękka / 2012 / 144 str.
Low-dropout regulators (LDRs) are indispensable components widely used in system-on-chip (SoC) designs to power up noise-sensitive blocks. With the proliferation of portable applications, LDRs are required to have accurate and fast regulation with low quiescent current consumption, compact chip area and without requiring any off-chip capacitors. This research focuses on the analysis and design of high-performance CMOS output-capacitor-free LDRs for SoC power management applications. Three different topologies: adaptively biased LDRs, adaptively biased LDRs with subthreshold undershoot-reduction, and LDRs with low-quiescent current and high power-supply-rejections are analyzed, designed and verified. They are powerful candidates for supplying different blocks of SoC: analog, mixed-signal, digital, and RF. Design-oriented and in-depth theoretical analysis is presented. With these topologies at hand, a cost-effective power management solution for SoC is easier-than-ever to construct.
Low-dropout regulators (LDRs) are indispensable components widely used in system-on-chip (SoC) designs to power up noise-sensitive blocks. With the proliferation of portable applications, LDRs are required to have accurate and fast regulation with low quiescent current consumption, compact chip area and without requiring any off-chip capacitors. This research focuses on the analysis and design of high-performance CMOS output-capacitor-free LDRs for SoC power management applications. Three different topologies: adaptively biased LDRs, adaptively biased LDRs with subthreshold undershoot-reduction, and LDRs with low-quiescent current and high power-supply-rejections are analyzed, designed and verified. They are powerful candidates for supplying different blocks of SoC: analog, mixed-signal, digital, and RF. Design-oriented and in-depth theoretical analysis is presented. With these topologies at hand, a cost-effective power management solution for SoC is easier-than-ever to construct.
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