Offset Reduction Techniques in High-Speed Analog-To-Digital Converters: Analysis, Design and Tradeoffs

ISBN-13: 9781402097157 / Angielski / Twarda / 2009 / 382 str.

Pedro M. Figueiredo; Joao C. Vital

Opis

Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.

Spis treści

Preface. List of Symbols and Abbreviations.

1 High-Speed ADC Architectures. 1.1 Introduction. 1.2 The Analog-to-Digital Converter. 1.3 Flash ADCs. 1.4 Two-Step Flash ADCs. 1.5 Folding and Interpolation ADCs. 1.6 Building Blocks of CMOS High-Speed ADCs.

2 Averaging Technique - DC Analysis and Termination. 2.1 Introduction. 2.2 Published Studies on the Averaging Technique. 2.3 Output Voltage and Gain. 2.4 Effect of Mismatches - INL and DNL. 2.5 Averaging in Folding Circuits. 2.6 Considerations About the Yield. 2.7 Termination of the Averaging Network.

3 Averaging Technique - Transient Analysis and Automated Design. 3.1 Introduction. 3.2 Flash ADC Architecture. 3.3 Output Voltage and Gain. 3.4 Effect of Mismatches. 3.5 Design of Averaged Pre-Amplifier Stages in Flash ADCs.

4 Integrated Prototypes using Averaging. 4.1 Introduction. 4.2 7-bit 120 MS/s I/Q flash ADC. 4.3 10-bit 100 MS/s Folding and Interpolation ADC.

5 Offset Cancellation Methods. 5.1 Introduction. 5.2 Offset Cancellation Techniques. 5.3 New Offset Cancellation Technique. 5.4 6-bit 1 GHz Two-Step Subranging ADC.

6 Conclusions. 6.1 Overview of the Research Work.

Appendix A Averaging with Piecewise Linear Differential Pairs. A.1 Introduction. A.2 Output Voltage and Gain. A.3 Effect of Mismatches - INL and DNL.

Appendix B Mismatches in the Resistors of the Aveaging Network. B.1 Introduction. B.2 Mismatches in Resistors R₀. B.3 Mismatches in Resistors R_1.

Appendix C Averaging in Folding Stages. C.1 Introduction. C.2 Equivalence Between Circular and Infinite Networks. C.3 Output Voltage and Gain. C.4 Effect of Mismatches.

References. Index.

O autorze

Pedro Figueiredo received the degrees of Licenciado and Doutor (PhD) in Electrical and Computer Engineering in 1999 and 2006, respectively, from the Instituto Superior Técnico (IST), Lisbon, Portugal. From 1997 to 1999, he was with the Analog and Mixed-Mode Circuits Group in the Institute for Systems and Computer Engineering (INESC), Lisbon, Portugal, where he worked on low-noise logic families and high-speed Analog-to-Digital Converters.
In 1999, he joined Chipidea - Microelectrónica, where he currently leads the group responsible for the design of Analog-to-Digital Converters. His main research interests are in the area of analog and mixed-signal circuits, with emphasis on high-speed data conversion and design automation. He has 10 publications in international journals and conferences.

João Vital received the degrees of Licenciado, Mestre and Doutor (PhD) in Electrical and Computer Engineering in 1986, 1990 and 1994, respectively, all from the Instituto Superior Técnico (IST), Lisboa, Portugal. He is a Co-founder of Chipidea - Microelectronica in 1997, and currently serves as Vice-President of Data Conversion, leading the Data Conversion Solutions Division of Chipidea to provide competitive solutions towards the demanding markets of Broadband Wireless Communications and Video. His main scientific interests are in the area of analog and mixed-signal integrated-circuit design, with a focus on data conversion. He developed research work in the University of Pavia, Italy, in the University of California - Los Angeles, USA, and in the Oregon State University, USA, also in 1990. He has over 50 publications in international journals, book chapters and conferences and is a co-holder of an European and US Patent filed by British Telecom.

Blurb

Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.

Since the offset voltages of the constituting sub-blocks of these converters (pre-amplifiers, folding circuits and latched comparators) present the definitive linearity limitation, the offset is the fundamental design parameter in high-speed CMOS ADCs. Consequently, offset reduction techniques must be employed, in order to achieve high frequency operation with low power and layout area. Averaging and offset sampling are the most widely used, both being thoroughly characterized:

• the most exhaustive study ever performed about averaging in both pre-amplifier and folding stages is presented, covering the DC and transient responses, all mismatch sources, termination, and a fully automated design procedure;
• existing offset sampling methods are carefully reviewed, and two new techniques are disclosed that, combined, yield a (nearly) offset free comparator.

Other relevant topics include kickback noise elimination in comparators, reference buffer design, a technique to compensate (certain) IR drops, details on the layout and floorplan of cascaded folding stages, and an improved scheme to select reference voltages in fine ADCs of two-step subranging converters. Special emphasis is given to the methods of guaranteeing specifications across process, temperature and supply voltage corners.