Modeling and Evaluation of Networks on Chip

ISBN-13: 9783659383823 / Angielski / Miękka / 2013 / 108 str.

Anjum Sheraz

Opis

The current process technologies are able to integrate billions of transistors on a single chip and the density of integration is even increasing. To effectively utilize the continuous increase in on-chip area there is a trend towards integration of more and more processing elements e.g. general-purpose processors, DSPs, memories, ASICs, reconfigurable hardware and custom hardware onto a single chip. The continuous increasing demand in number of on-chip resources has lead the SoC researchers to design scalable, modular and efficient on-chip communication infrastructures known as networks on chip (NoC). Design and selection of appropriate architecture, routing algorithm, router micro-architecture and mapping techniques for on-chip communication has a key role in the design and implementation of the complete platform for NoC. This book contributes by presenting two simulation models and then applying these models on some proposed generic as well as application specific efficient, scalable and optimized architectures & routing algorithms for on-chip communication.

O autorze

Sheraz Anjum, PhD: Microelectronics and Solid-State Electronics from Institute of Microelectronics, Graduate University of Chinese Academy of Sciences, Beijing, China. Associate Professor at the Department of Electrical Engineering, COMSATS Institute of Information Technology, Wah Cantt Pakistan.