Formal Verification: An Essential Toolkit for Modern VLSI Design

ISBN-13: 9780128007273 / Angielski / Miękka / 2015 / 408 str.

Seligman, Erik

Opis

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.

• Learn formal verification algorithms to gain full coverage without exhaustive simulation
• Understand formal verification tools and how they differ from simulation tools
• Create instant test benches to gain insight into how models work and find initial bugs
• Learn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems

Recenzje

"...the authors thoroughly expressed their practical knowledge of this complex, and misunderstood topic, in an easy to read presentation...I strongly recommend this book to design and verification engineers who are contemplating, or are currently using formal verification..." --VerificationAcademy.com

Spis treści

1. Formal Verification: From Dreams to Reality
2. Basic Formal Verification Algorithms
3. Introduction to SystemVerilog Assertions
4. Formal Property Verification
5. Effective FPV For Design Exercise
6. Effective FPV for Verification
7. FPV "Apps” for Specific SOC Problems
8. Formal Equivalence Verification
9. Formal Verification's Greatest Bloopers: The Danger of False Positives
10. Dealing with Complexity
11. Your New FV-Aware Lifestyle

O autorze

Erik Seligman is currently a Senior Product Engineering Architect at Cadence Design Systems, where he helps to plan and support the Jasper Formal Verification tool suite. Previously he worked at Intel Corporation in Hillsboro, Oregon for over two decades, in a variety of positions involving software, design, simulation, and formal verification. In his spare time he hosts the "Math Mutation” podcast, and has served as an elected director on the Hillsboro school board. Tom Schubert is on the Electrical and Computer Engineering faculty at Portland State University and directs a graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intel's largest pre-silicon validation formal verification team develop and apply FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis. M. V. Achutha Kiran Kumar is an Intel Fellow in the Design Engineering group at Intel and leads the company's Formal Verification Central Technology Office, one of the largest industrial Formal Verification teams in the world. He has over 20 years experience where he worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation, and various levels of validation including formal verification.