Design for Testability, Debug and Reliability: Next Generation Measures Using Formal Techniques

ISBN-13: 9783030692117 / Angielski / Miękka / 2022

Sebastian Huhn;Rolf Drechsler

Opis

This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces.

Spis treści

Introduction.- Integrated Circuits.- Formal Techniques.- Embedded Compression Architecture for Test Access Ports.- Optimization SAT-based Retargeting for Embedded Compression.- Reconfigurable TAP Controllers with Embedded Compression.- Embedded Multichannel Test Compression for Low-Pin Count Test.- Enhanced Reliability using Formal Techniques.- Conclusion and Outlook.

O autorze

Sebastian Huhn is currently a PostDoc at the Group of Computer Engineering, University of Bremen, Germany. Sebastian Huhn received his bachelor's (master) degree in 2012 (2014) in computer engineering from the University of Bremen and his doctoral (Dr.-Ing.) degree in 2020. Besides this, he is a senior researcher at the German Research Center for Artificial Intelligence (DFKI). His research interests include test interfaces, formal methods, formal solving techniques, pattern retargeting, and reliability analysis or enhancement of circuits. He has been in the Program Committee of the International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) since 2018, the International Conference on Advances in System Testing and Validation Lifecycle (VALID), IEEE European Test Symposium (ETS) and IEEE/ACM International Conference On Computer Aided Design (ICCAD) since 2020.

Rolf Drechsler is head of Cyber-Physical Systems department at the German Research Center for Artificial Intelligence (DFKI) since 2011. Furthermore, he is a Full Professor at the Institute of Computer Science, University of Bremen, since 2001. Before, he worked for the Corporate Technology Department of Siemens AG, and was with the Institute of Computer Science, Albert-Ludwig University of Freiburg/Breisgau, Germany. Rolf Drechsler received the Diploma and Dr. Phil. Nat. degrees in computer science from the Goethe-University in Frankfurt/Main, Germany, in 1992 and, respectively, 1995. Rolf Drechsler focusses in his research at DFKI and in the Group for Computer Architecture, which he is heading at the Institute of Computer Science of the University of Bremen, on the development and design of data structures and algorithms with an emphasis on circuit and system design

Blurb

This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces.

• Provides readers with a combination of a comprehensive set of formal techniques covering and enhancing different aspects of the state-of-the-art design and test flow for ICs;

• Introduces newly developed heuristic, formal optimization-based and partition-based retargeting techniques and integrates them into a common framework;

• Describes fully compliant (with respect to industrial de-facto standard) measures to enhance the DFT, DFD and DFR capabilities while supporting standardized data exchange formats;

• Includes new measures to tackle shortcomings of existing state-of-the-art methods, including zero-defect enforcing safety-critical applications.